Switching power supply for low step down conversion ratio with reduced switching losses

ABSTRACT

Disclosed herein is a power converter with low step down conversion ratio with improved power conversion efficiency. The power converter includes a first inductor to receive the input voltage, and a second inductor to supply the output voltage to a load. The first inductor and the second inductor are electromagnetically coupled to each other. The power converter further includes a first switch coupled between the first inductor and the second inductor. The first switch is switched according to a pulse having a frequency corresponding to a resonant frequency of (i) a series inductance between the first inductor and the second inductor and (ii) a parallel capacitance across the first switch. The power converter further includes a second switch coupled to the first switch and the second inductor to supply a reference voltage to the second inductor according to another pulse having the frequency.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. patent applicationSer. No. 15/680,033, filed Aug. 17, 2017, now U.S. Pat. No. 10,298,132,which application claims priority to U.S. Provisional Application No.62/407,970 filed Oct. 13, 2016, all such applications being incorporatedby reference herein in their entirety.

TECHNICAL FIELD

Embodiments of the present disclosure relate generally to powerconverters, and more particularly to switching power convertersutilizing a tapped (coupled) inductor to achieve low step downconversion ratio, and utilizing parasitic inductance and capacitance toreduce switching loss, hence, improve power conversion efficiency.

BACKGROUND

A power converter is a circuit component that supplies electric powerfrom a power source to a load. Some power converter converts a directcurrent (DC) voltage from a power source into a lower DC voltage toprovide the lower DC voltage to a load. For example, a power converterreceives a high direct current (DC) voltage (e.g., 50V) from a powersource, and converts the high DC voltage into a lower DC voltage (e.g.,1V) for powering consumer electronics (e.g., laptops, tablet computers,mobile phones, or any electronic circuit).

Some power converters implement transformers or tapped inductors toimprove a step down conversion ratio capability from the DC inputvoltage to the DC output voltage. In particular, energy transferredthrough electromagnetic coupling between two inductors in a switchingpower converter allows a large voltage difference between the DC inputvoltage and the DC output voltage. However, leakage inductance (alsoreferred to as a parasitic inductance herein) of the tapped inductorsmay induce high voltage spikes or oscillations across the switchingdevices. Such voltage spikes or oscillations may result in power loss,and reduce power conversion efficiency. Moreover, such voltage spikes oroscillations may increase radiated electromagnetic interference (EMI)noise.

SUMMARY

The present embodiments relate generally to a switching power converterwith low step down ratio capability. In one or more embodiments, theswitching power converter implements electromagnetically coupledinductors for improving (or reducing) step down conversion ratio betweenan input voltage and an output voltage, where a parasitic inductance ofthe electromagnetically coupled inductors is resonated with acapacitance such that switching devices can be turned on when voltagesacross the switching devices are approximately zero voltage.

In accordance with these and other aspects, embodiments disclosed hereininclude a power converter to convert an input voltage into an outputvoltage. In one or more embodiments, the power converter includes: afirst inductor to receive the input voltage; a second inductorelectromagnetically coupled to the first inductor, the second inductorto supply the output voltage to a load; a first switch coupled betweenthe first inductor and the second inductor, the first switch beingswitched according to a pulse having a frequency corresponding to aresonant frequency of (i) a series inductance between the first inductorand the second inductor and (ii) a parallel capacitance across the firstswitch; and a second switch coupled to the first switch and the secondinductor to supply a reference voltage to the second inductor accordingto another pulse having the frequency.

One or more embodiments disclosed herein are related to a method forconverting an input voltage into an output voltage. In one or moreembodiments, the method includes controlling switching devices forperiodically coupling the input voltage to the output voltage. Themethod further includes interposing electromagnetically coupledinductors for improving a step down conversion ratio between the inputvoltage and the output voltage. The method further includes configuringa parasitic inductance of the electromagnetically coupled inductors soas to resonate with a capacitance such that the switching devices can beturned on when voltages across the switching devices are approximatelyzero voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and features of the present embodiments willbecome apparent to those ordinarily skilled in the art upon review ofthe following description of specific embodiments in conjunction withthe accompanying figures, wherein:

FIG. 1 is a block diagram of an example switching power converter,according to one or more embodiments;

FIG. 2A illustrates example timing diagrams of pulses to operate aswitching power supply, according to one or more embodiments;

FIG. 2B is an example plot showing voltage spikes due to parasiticinductance, according to one or more embodiments.

FIG. 3 illustrates example timing diagrams showing operating conditionsof the switching power converter of FIG. 1, according to one or moreembodiments.

DETAILED DESCRIPTION

The present embodiments will now be described in detail with referenceto the drawings, which are provided as illustrative examples of theembodiments so as to enable those skilled in the art to practice theembodiments and alternatives apparent to those skilled in the art.Notably, the figures and examples below are not meant to limit the scopeof the present embodiments to a single embodiment, but other embodimentsare possible by way of interchange of some or all of the described orillustrated elements. Moreover, where certain elements of the presentembodiments can be partially or fully implemented using knowncomponents, only those portions of such known components that arenecessary for an understanding of the present embodiments will bedescribed, and detailed descriptions of other portions of such knowncomponents will be omitted so as not to obscure the present embodiments.In the present specification, an embodiment showing a singular componentshould not be considered limiting; rather, the present disclosure isintended to encompass other embodiments including a plurality of thesame component, and vice-versa, unless explicitly stated otherwiseherein. Moreover, applicants do not intend for any term in thespecification or claims to be ascribed an uncommon or special meaningunless explicitly set forth as such. Further, the present embodimentsencompass present and future known equivalents to the known componentsreferred to herein by way of illustration.

Overview

According to certain general aspects, a switching power converter withlow step down ratio capability is described. More particularly, theswitching power converter implements electromagnetically coupledinductors for improving (or reducing) step down conversion ratio betweenan input voltage and an output voltage, where a parasitic inductance ofthe electromagnetically coupled inductors is resonated with acapacitance such that switching devices can be turned on when voltagesacross the switching devices are approximately zero voltage.

In one or more embodiments, the switching power converter includes afirst inductor and a second inductor electromagnetically coupled to eachother, a first switch coupled between the first inductor and the secondinductor, and a second switch coupled to the first switch and the secondinductor. The first switch is switched according to a pulse controlledby a feedback circuit to regulate the output voltage to a desired level.The second switch may be switched complementarity to the first switch.As a result, the disclosed switching power converter enables a largevoltage difference between the input voltage and the output voltagethrough electromagnetic coupling between two inductors.

In one aspect, the series inductance includes at least a parasiticinductance of the first inductor. Thus, the parasitic inductance may beselected to resonate with a capacitance (e.g., a parasitic capacitance,an intentional capacitance of a capacitor or a combination of them).Resonating of the parasitic inductance and the capacitance causes thevoltage across a switching device to have a sinusoidal wave shape, whichhelps reduce voltage spikes. The sinusoidal wave shape across thecapacitance allows the switching device to be turned on with a lowvoltage across the switching device (e.g., 0-1.0V), thereby obviatingpower loss. As a result, the disclosed switching power converter enablesa large voltage difference between the input voltage and the outputvoltage through electromagnetic coupling between two inductors withimproved power conversion efficiency.

Example Switching Power Converter

FIG. 1 is a block diagram of an example switching power converter 100,according to one or more embodiments. The switching power converter 100is coupled to a power source 110 and a load 120 through conductive linesor traces, for example. The power source 110 may be a battery, poweroutlet, a power adapter, or any circuit supplying an input voltage tothe switching power converter 100. The load 120 may be a laptop, atablet computer, a mobile phone, or any electronic circuit receiving anoutput voltage from the switching power converter 100. The switchingpower converter 100 receives the DC input voltage, converts the DC inputvoltage into the DC output voltage, and supplies the output voltage tothe load 120. In one aspect, the switching power converter 100 performsa voltage conversion with a small step down ratio (e.g., less than 1/50to 1/5) between the input voltage and the output voltage with improvedpower conversion efficiency. A step down ratio herein refers to a ratiobetween a DC output voltage and a DC input voltage (i.e., Vout/Vin).

In one or more embodiments, the switching power converter 100 includes afirst inductor L1, a second inductor L2, a series inductance Lp, aparallel capacitance Cp, a first transistor Q1, a second transistor Q2,a driver 130, and an output capacitor Cout. These components may beimplemented as an integrated circuit, discrete components on a printedcircuit board, or any combination of them. These components operatetogether to convert the DC input voltage from the power source 110 intoa DC output voltage, and supply the DC output voltage to the load 120.In some embodiments, the switching power converter 100 includesdifferent, fewer, or additional components or in different arrangementsthan shown in FIG. 1. For example, the driver 130, the output capacitorCout, or both may be implemented as external components separate fromother components of the switching power converter 100.

In one aspect, the components of the switching power converter 100 areconfigured as a zero voltage switching tapped inductor buck converter.In one implementation, the first inductor L1 may be coupled to the powersource 110 at node n1 and is coupled to a series inductance Lp at noden2. The series inductance Lp is coupled to a first transistor Q1 and aparallel capacitance Cp at node n3. The first transistor Q1 and theparallel capacitance Cp are coupled to the second inductor L2 and thesecond transistor Q2 at node n4. The second inductor L2 is coupled tothe output capacitor Cout at node n5 and may be coupled to the load 120.The second transistor Q2 and the output capacitor Cout are coupled to areference terminal 150 at which a reference voltage (e.g., groundvoltage) is supplied. The first transistor Q1 and the second transistorQ2 are coupled to the driver 130 at nodes n6, n7, respectively.

The first inductor L1 and the second inductor L2 are circuit componentscoupled between an input and an output of the switching power converter100. In one configuration, the first inductor L1 includes one endcoupled to the node n1 and another end coupled to the node n2, and thesecond inductor L2 includes one end coupled to the node n5 and anotherend coupled to the node n4. The first inductor L1 may receive a DC inputvoltage for the switching power converter 100 at the node n1, and thesecond inductor L2 may supply a DC output voltage for the switchingpower converter 100 at the node n5. The inductors L1, L2 may beimplemented as a coupled or tapped inductors, thus the inductors L1, L2are electromagnetically coupled to each other. In one aspect, a numberof turns of the first inductor L1 and a number of turns the secondinductor L2 determine a step down ratio as shown in Eq. (1) below:

$\begin{matrix}{{{Step}\mspace{14mu} {Down}\mspace{14mu} {Ratio}} = {\frac{Vout}{Vin} = \frac{T_{on}N_{2}}{{T_{off}N_{1}} + {( {T_{on} + T_{off}} )N_{2}}}}} & {{Eq}.\mspace{14mu} (1)}\end{matrix}$

where N1 is a number of turns (or windings) of the first inductor L1 andN2 is a number of turns (or windings) of the second inductor L2, Ton isa duration of the on-time of the transistor Q1, and Toff is a durationof the off-time of the transistor Q1.

The series inductance Lp is a circuit model coupled between theinductors L1, L2. The series inductance Lp includes one end coupled tothe node n2 and another end coupled to the node n3. The seriesinductance Lp includes at least a parasitic inductance (also referred toas a “leakage inductance” herein) of the tapped (coupled) inductor. Theseries inductance Lp may additionally include an inductance of adiscrete inductor physically coupled between the nodes n2, n3, in serieswith the leakage inductance. In case the additional discrete inductor isimplemented, the series inductance Lp represents a sum of the parasiticinductance and the inductance of the discrete inductor.

The first transistor Q1 is a circuit component coupled between theseries inductance Lp and the inductor L2. In one approach, the firsttransistor Q1 is implemented as an n-type or a p-type field effecttransistor (i.e. MOSFET). The first transistor Q1 may be implemented asanother type of switching power transistor. The first transistor Q1includes a first end (e.g., drain) coupled to the node n3, a second end(e.g., source) coupled to the node n4, and a third end (e.g., gate)coupled to the node n6. In one aspect, the first transistor Q1 operatesas a switch electrically coupling or decoupling the node n3 to the noden4, according to a control signal applied at the node n6. Specifically,the first transistor Q1 electrically couples the node n3 to the node n4,in response to a voltage at the node n6 being a first voltage.Similarly, the first transistor Q1 electrically decouples the node n3from the node n4, in response to a voltage at the node n6 being a secondvoltage. By implementing the first transistor Q1 between the nodes n3,n4, the implementation of the driver 130 can be simplified.

The parallel capacitance Cp is a circuit model coupled in parallelacross two ends (e.g., drain and source) of the first transistor Q1. Theparallel capacitance Cp includes one end coupled to the node n3 andanother end coupled to the node n4. The parallel capacitance Cp includesat least a parasitic capacitance of the first transistor Q1. Theparallel capacitance Cp may additionally include a capacitance of adiscrete capacitor physically coupled between the nodes n3, n4, inparallel with the parallel capacitance Cp. In case the additionaldiscrete capacitor is implemented, the parallel capacitance Cprepresents a sum of the parasitic capacitance and the capacitance of thediscrete capacitor. In one aspect, the parallel capacitance Cp resonateswith the series inductance Lp at a resonant frequency of the parallelcapacitance Cp and the series inductance Lp to help reduce the turn-ontransition losses of the first transistor Q1 and hence improve powerconversion efficiency as described in detail below with respect to FIGS.2 through 4.

The second transistor Q2 is a circuit component coupled to the firsttransistor Q1 and the second inductor L2. In one approach, the secondtransistor Q2 is implemented as an n-type or a p-type field effecttransistor (i.e. MOSFET). The second transistor Q2 may be implemented asanother type of switching power transistor. The second transistor Q2includes a first end (e.g., drain) coupled to the node n4, and a secondend (e.g., source) coupled to the reference terminal 150. In one aspect,the second transistor Q2 operates as a switch electrically coupling ordecoupling the node n4 to the reference terminal 150, according toanother control signal applied at the node n7. Specifically, the secondtransistor Q2 electrically couples the node n4 to the reference terminal150, in response to a voltage at the node n7 being a first voltage.Similarly, the second transistor Q2 electrically decouples the node n4from the reference terminal 150, in response to a voltage at the node n7being a second voltage.

The driver 130 is a circuit component that generates signals foroperating the first transistor Q1 and the second transistor Q2. Thedriver 130 includes a first output coupled to the node n6 and a secondoutput coupled to the node n6. In one aspect, the driver 130 generatespulses at a particular frequency, and applies the pulses to the nodesn6, n7 (e.g., each having a corresponding pulse width). In one approach,the driver 130 generates pulses to turn on the first transistor Q1 andturn off the second transistor Q2 during a first time period, and turnoff the first transistor Q1 and turn on the second transistor Q2 duringa second time period. In case the first transistor Q1 is implemented asan n-type transistor and the second transistor Q2 is implemented as ap-type transistor, or the first transistor Q1 is implemented as a p-typetransistor and the second transistor Q2 is implemented as an n-typetransistor, the nodes n6, n7 may be coupled to each other and the driver130 may output a single pulse. Example pulses generated by the driver130 and operations of the switching power converter 100 are providedbelow with respect to FIGS. 2 and 3.

Referring to FIG. 2A, illustrated are example timing diagrams of pulsesVn6, Vn7 to operate the switching power supply 100, according to one ormore embodiments. In an embodiment in which the first transistor Q1 andthe second transistor Q2 are implemented as n-type transistors, thedriver 130 generates a first pulse Vn7 applied to the second transistorQ2 at the node n7 and a second pulse Vn6 applied to the first transistorQ1 at the node n6. The pulses Vn6, Vn7 are synchronized with a frequencyor a time period T_SW between time T0 and T2. Within the time periodT_SW, the pulse Vn6 has a high voltage and the pulse Vn7 has a lowvoltage during a time period between T0 and T1. In addition, the pulseVn6 has a low voltage and the pulse Vn7 has a high voltage during a timeperiod between T1 and T2. Accordingly, the first transistor Q1 is turnedon and the second transistor Q2 is turned off during the time periodbetween T0 and T1 (i.e., Ton of Q1), and the first transistor Q1 isturned off and the second transistor Q2 is turned on during the timeperiod between T1 and T2 (i.e., Toff of Q1).

During the time period between T0 and T1, current flowing through boththe first and second inductor L1, L2 increases, allowing energy to bestored at the second inductor L2, and the leakage inductance Lp. Duringthe time period between T1 and T2, the stored energy in the secondinductor L2 is transferred to the load. At the same time the storedenergy in the leakage inductor Lp induces a resonance between theleakage inductor Lp and the parallel capacitance Cp. Assuming that thefirst inductor L1 and the series inductance Lp were omitted, a voltagedifference or a step down ratio between the input voltage and the outputvoltage becomes proportional to a duty cycle of the pulses Vn6, Vn7. Forexample, a narrower time period between T0 and T1 (i.e. a smaller pulsewidth) allows the smaller step down conversion ratio.

To further improve a step down ratio beyond using a smaller pulse width,the first inductor L1 electromagnetically coupled to the second inductorL2 may be implemented. The turn ratio of the inductor windings N1/N2allows the voltages across the inductors L1 and L2 to be coupledtogether and distributed between the inductors L1 and L2. In particular,the larger number N1 of windings of the first inductor L1 compared tothe number N2 of windings of the second inductor L2 allows a lower stepdown ratio for the given pulse width that determines Ton and Toff, asshown in Eq. (1) above. As a result, a smaller step down ratio can beobtained by implementing the first inductor L1 electromagneticallycoupled to the second inductor L2 compared to when the first inductor L1is omitted.

The present applicants recognize that, although the first inductor L1magnetically coupled to the second inductor L2 allows a smaller stepdown conversion ratio from the input voltage to the output voltage, aparasitic inductance of the tapped (coupled) inductor may introducevoltage spikes or oscillations. For example, FIG. 2B illustrates a plotshowing a voltage at the node n3, in case the parallel capacitance Cp istoo small (e.g., a few fF). As shown in FIG. 2B, voltage peaks 210 asshown in FIG. 2B may occur during the time period between T1 and T2 dueto the parasitic inductance of the first inductor L1. These voltagepeaks 210 result in power loss, thereby reducing power conversionefficiency. In addition, the voltage peaks 210 may increase radiatedelectromagnetic interference (EMI) noise.

In one or more embodiments, the parallel capacitance Cp is determined toresonate with the parasitic inductance or the series inductance Lpincluding the parasitic inductance. As described above with respect toFIG. 1, the parallel capacitance Cp may be a parasitic capacitance ofthe first transistor Q1, or a combination of the parasitic capacitanceand a capacitance of a discrete capacitor coupled between the nodes n3,n4 across the first transistor Q1. The parallel capacitance Cp may beselected to resonate with the series inductance Lp such that theoff-time Toff of the transistor Q1 from Eq. (1) is substantially equalto a half of the resonant period (i.e., an inverse of the resonantfrequency of the parallel capacitance Cp and the series inductance Lp),or as shown in Eq. (2) below:

$\begin{matrix}{C_{P} = {\frac{1}{L_{P}}( \frac{T_{off}}{\pi} )^{2}}} & {{Eq}.\mspace{14mu} (2)}\end{matrix}$

Accordingly, the voltage across the parallel capacitor Cp (transistorQ1) has a sinusoidal wave shape. The voltage spikes may be suppressed.The transistor Q1 can be turned on with low voltage across a drain and asource of the transistor Q1 (e.g., 0-1.0V), and hence power loss can bereduced. Moreover, electromagnetic interference (EMI) noise due to thevoltage spikes or oscillation can be decreased.

Referring to FIG. 3, illustrated are example timing diagrams showingoperating conditions of the switching power converter 100 of FIG. 1,according to one or more embodiments. In FIG. 3, a voltage plot Vn4 atnode n4, a voltage plot VCp across the first transistor Q1 (or theparallel capacitance Cp), and a current plot ILp through the seriesinductance Lp, in response to the pulses Vn6, Vn7 applied from thedriver 130 are shown. By implementing the parallel capacitance Cp andapplying the pulses Vn6, Vn7 as shown in FIG. 3, the transistor Q1 canbe turned on with low voltage across the transistor Q1, therebydecreasing power loss.

In one or more embodiments, the pulses Vn6, Vn7 are applied inaccordance with a resonant frequency of the parallel capacitance Cp andthe series inductance Lp. In one approach, the parallel capacitance Cpand the series inductance Lp resonate with each other at a resonantfrequency as shown in the voltage plot VCp and the current plot ILp.During the time period between T0 and T1, the first transistor Q1 may beturned on and the second transistor Q2 may be turned off, when the VCpis substantially equal to 0V or within a particular range (e.g.,0-0.5V), or when a voltage at the node n3 and a voltage at the node n4are substantially equal to each other. Accordingly, a current path fromthe power source 110 to the load 120 through the first transistor Q1 isenabled during the time period between T0 and T1, with a reduced voltagedrop across the first transistor Q1. Turning on the first transistor Q1with a reduced voltage across the nodes n3, n4 reduces the lossesassociated with turning-on of the transistor Q1. In one aspect, thevoltage at node n3 corresponds to a sum of the voltage at node n4 andthe voltage across the parallel capacitance Cp. The series inductance Lpand the parallel capacitance Cp can resonate with each other during thetime period between T1 and T2. During the time period between T1 and T2,the first transistor Q1 may be turned off and the second transistor Q2may be turned on. At time T1, when the first transistor Q1 is turnedoff, the energy stored in the series inductance Lp is smoothlytransferred to the parallel capacitance Cp. Hence, voltage spikes oroscillation shown in FIG. 2B are reduced by implementing the parallelcapacitance Cp, the series inductance Lp and switching the transistorsQ1, Q2 as shown in FIGS. 1 and 3.

Advantageously, the disclosed switching power converter can achieve 3-4%higher power conversion efficiency than a conventional tapped inductorpower converter employing a zero voltage switching using a conventionaltapped inductor. In addition, the disclosed switching power convertercan achieve 7-8% higher power conversion efficiency than a conventionalbuck power converter. Accordingly, the disclosed switching powerconverter 100 can improve power conversion efficiency with a smallerstep down ratio (e.g., less than 10) and with a reduced energy loss dueto the parasitic inductance of the first inductor of L1.

The construction and arrangement of the systems and methods as shown inthe various exemplary embodiments are illustrative only. Although only afew embodiments have been described in detail in this disclosure, manymodifications are possible (e.g., variations in sizes, dimensions,structures, shapes and proportions of the various elements, values ofparameters, mounting arrangements, use of materials, colors,orientations, etc.). For example, the position of elements may bereversed or otherwise varied and the nature or number of discreteelements or positions may be altered or varied. Accordingly, all suchmodifications are intended to be included within the scope of thepresent disclosure. The order or sequence of any process or method stepsmay be varied or re-sequenced according to alternative embodiments.Other substitutions, modifications, changes, and omissions may be madein the design, operating conditions and arrangement of the exemplaryembodiments without departing from the scope of the present disclosure.

What is claimed is:
 1. A power converter to convert an input voltageinto an output voltage, the power converter comprising: a first inductorcomprising one end of the first inductor to receive the input voltage; asecond inductor electromagnetically coupled to the first inductor, thesecond inductor comprising one end of the second inductor coupled to aload, the one end of the second inductor to supply the output voltage tothe load; a first switch coupled between another end of the firstinductor and another end of the second inductor, the first switch beingswitched according to a pulse having a frequency corresponding to aresonant frequency of (i) a series inductance between the another end ofthe first inductor and the another end of the second inductor and (ii) aparallel capacitance across one end the first switch and another end ofthe first switch; and a second switch comprising one end of the secondswitch coupled to the another end of the first switch and the anotherend of the second inductor, the second switch to supply a referencevoltage to the another end of the second inductor according to anotherpulse having the frequency.
 2. The power converter claim 1, furthercomprising: a driver configured to apply the pulse to the first switchand apply the another pulse to the second switch, the first switch toturn on during a first time period and turn off during a second timeperiod according to the pulse, the second switch to turn off during thefirst time period and turn on during the second time period according tothe another pulse.
 3. The power converter of claim 2, wherein the driveris configured to turn on the first switch and turn off the second switchduring the first time period, while a voltage at the one end of thefirst switch is substantially equal to a voltage at the another end ofthe first switch.
 4. The power converter of claim 3, wherein the firsttime period is substantially equal to a half of a resonant period, theresonant period being an inverse of the resonant frequency.
 5. The powerconverter of claim 1, wherein the series inductance is a parasiticinductance of the first inductor.
 6. The power converter of claim 1,wherein the series inductance is a combination of a parasitic inductanceof the first inductor and an inductance of a discrete inductor coupledin series between the first inductor and the first switch.
 7. The powerconverter of claim 1, wherein the parallel capacitance is a parasiticcapacitance of the first switch.
 8. The power converter of claim 1,wherein the parallel capacitance is a combination of a parasiticcapacitance of the first switch and a capacitance of a discretecapacitor in parallel with the first switch between the one end of thefirst switch and the another end of the first switch.
 9. The powerconverter of claim 1, wherein the input voltage is a first directcurrent voltage and the output voltage is a second direct currentvoltage lower than the first direct current voltage.
 10. The powerconverter of claim 1, wherein a turn ratio of the first inductor and thesecond inductor corresponds to a ratio between the input voltage and theoutput voltage.
 11. The power converter of claim 1, wherein the firstswitch and the second switch are n-type transistors.
 12. The powerconverter claim 1, wherein the reference voltage is a ground voltage.13. A power converter to convert an input voltage into an outputvoltage, the power converter comprising: switching devices forperiodically coupling the input voltage to the output voltage; andelectromagnetically coupled inductors for improving a step downconversion ratio between the input voltage and the output voltage,wherein a parasitic inductance of the electromagnetically coupledinductors is resonated with a capacitance such that the switchingdevices can be turned on when voltages across the switching devices areapproximately zero voltage.
 14. The power converter of claim 13, whereinthe electromagnetically coupled inductors include: a first inductor toreceive the input voltage; and a second inductor electromagneticallycoupled to the first inductor, the second inductor to supply the outputvoltage to a load; and wherein the switching devices include: a firstswitch coupled between the first inductor and the second inductor, thefirst switch being switched according to a pulse having a frequencycorresponding to a resonant frequency of (i) a series inductance betweenthe first inductor and the second inductor and (ii) a parallelcapacitance across the first switch; and a second switch coupled to thefirst switch and the second inductor to supply a reference voltage tothe second inductor according to another pulse having the frequency. 15.The power converter of claim 14, further comprising: a driver configuredto apply the pulse to the first switch and apply said another pulse tothe second switch, the first switch to turn on during a first timeperiod and turn off during a second time period according to the pulse,the second switch to turn off during the first time period and turn onduring the second time period according to said another pulse.
 16. Thepower converter of claim 15, wherein the driver is configured to turn onthe first switch and turn off the second switch during the first timeperiod, while a voltage at one end of the first switch is substantiallyequal to a voltage at another end of the first switch.
 17. The powerconverter of claim 16, wherein the first time period is substantiallyequal to a half of a resonant period, the resonant period being aninverse of the resonant frequency.
 18. The power converter of claim 14,wherein the series inductance is the parasitic inductance of the firstinductor or a combination of the parasitic inductance and an inductanceof a discrete inductor coupled in series between the first inductor andthe first switch.
 19. The power converter of claim 14, wherein theparallel capacitance is a parasitic capacitance of the first switch or acombination of the parasitic capacitance and a capacitance of a discretecapacitor in parallel with the first switch between the first inductorand the second inductor.
 20. A method for converting an input voltageinto an output voltage, comprising: controlling switching devices forperiodically coupling the input voltage to the output voltage;interposing electromagnetically coupled inductors for improving a stepdown conversion ratio between the input voltage and the output voltage;and configuring a parasitic inductance of the electromagneticallycoupled inductors so as to resonate with a capacitance such that theswitching devices can be turned on when voltages across the switchingdevices are approximately zero voltage.